Lattrex Inc.

Taped out · first silicon Nov 2026

Kyttar: a clockless, massively parallel processor for real-time signal processing.

A homogeneous array of self-timed compute cells with no global clock. It runs DSP, many channels at once, at a fraction of the power of an FPGA, and it is programmed at the function level instead of in HDL. A 120-cell prototype is in fabrication now.

See the architecture Program it with placeKYT

120-cell prototype · SkyWater SKY130

First silicon Nov 2026

Toolchain open source today

The Kyttar prototype chip layout: a dense array of asynchronous compute cells filling the die core, surrounded by the I/O pad ring, as taped out on the SkyWater SKY130 process

The Kyttar prototype as taped out on SKY130 (120-cell array, in the Caravel/OpenFrame harness).

How it works

Three steps from a block diagram to a running, debuggable design, no hardware-description language, no timing closure, no manual layout.

Build in GNU Radio

Compose your signal chain in GNU Radio Companion using Kyttar DSP blocks, the workflow SDR engineers already know.

Place, route, build

Import it into placeKYT. It maps your block graph onto the 2D cell array, routes it, and builds a bitstream automatically.

Run & debug

Simulate it cycle-accurately against real signal data, set breakpoints, single-step, and inspect any cell, live.

Why placeKYT

The whole point is a shorter, more transparent loop. You see exactly what your design does on the hardware, because the thing you debug is the thing that runs.

GNU Radio to Bitstream

Build your design in GNU Radio Companion, import it, and placeKYT turns it into a running bitstream on the cell array, with output back into GNU Radio's own waveform viewer. No HDL, no timing closure, no manual layout.

Instruction-Level Debug

Set breakpoints, single-step execution, and inspect any cell's state and memory while it runs. Debug your signal processing at the assembly level, not by reading waveforms off a synthesized HDL netlist.

Automated Place & Route

placeKYT maps your DSP block graph onto the 2D cell array, optimizes placement, and inserts routing automatically, so reconfiguring a signal chain is an edit-and-rebuild, not a re-layout.

Cycle-Accurate Simulation

Run the design against real signal data on a cycle-accurate model of the chip, and watch data flow through the fabric in real time.

Get placeKYT on GitHub → Early alpha: works end to end for the included examples, built solo, with rough edges and more blocks landing. Open source and free. Installs from source on Linux today; one-file Windows / macOS builds coming soon. Experimenters welcome.

The architecture underneath

The easy workflow is possible because of what Kyttar is: a clockless, massively parallel cell array purpose-built for real-time DSP. This is the payoff under the hood.

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Clockless

No global clock. No clock distribution network. No clock skew. Each cell operates asynchronously, processing data the instant it arrives. The result: power proportional to activity, deterministic latency, and no clock-harmonic noise injected into sensitive analog and RF front-ends.

✥

Massively Parallel

An array of identical compute cells, each with its own memory, ALU, and bundled-data communication with its four neighbors. No shared bus. No central bottleneck. Every cell runs its own program independently, in parallel.

≡

Signal Processing

Purpose-built for real-time DSP. Hardware multiply-accumulate. Q15 fixed-point arithmetic. Run many parallel receiver chains, demodulators, filters, mixers, decoders, simultaneously on a single chip.

→

Reconfigurable On the Fly

Compose DSP functions by placing them spatially across the array, then reconfigure in microseconds with a register write, without halting the data plane. Integrated with GNU Radio for real-world SDR workflows.

FPGA-Class DSP, Without the FPGA Tradeoffs

	Classical DSP	FPGA	Kyttar
Parallelism	Limited (sequential core)	Massive	Massive (spatial cell array)
Programming model	C / assembly	HDL (VHDL / Verilog)	Function-level block placement
Reconfiguration	Software reload	Bitstream rebuild (hours)	Register write (microseconds), in-flight
Power	Moderate	High (clock-tree floor)	Low (clockless, activity-proportional)
Clock noise into analog/RF	Yes	Yes	None (fully asynchronous)
Fault tolerance	None	Limited	Cell-level route-around
Raw peak throughput	Lower	Very high	Competitive (scales with node and array size)

The FPGA wins on raw peak throughput and decades of ecosystem maturity. Kyttar wins on the combination, parallelism with far lower power, no clock noise, microsecond in-flight reconfiguration, and a function-level programming model that skips HDL and timing closure entirely.

Applications

Software-Defined Radio

Many parallel channels of demodulation on one low-power chip. Wideband monitoring, cognitive radio, and multi-mode receivers that reconfigure on the fly.

Defense & Intelligence

Low-SWaP spectrum awareness and cognitive electronic warfare. Tactical communications processing in a man-portable, power-constrained package.

Commercial & Instrumentation

Multi-channel base-station and radar processing, test and measurement, and reconfigurable digital signal processing for mixed-signal systems.

About

Lattrex Inc. designs asynchronous parallel processors for real-time signal processing, a homogeneous array of self-timed cells that runs DSP functions in parallel, with no global clock.

Our first chip, a 120-cell prototype, taped out on the SkyWater 130nm process in 2026 using an open-source design flow, with first silicon expected back in November 2026. The architecture is process-portable and scales to advanced nodes where thousands of cells enable full-spectrum signal processing; the production target is a 12nm FinFET process.

Lattrex is a Delaware C-corporation operating in Tennessee, registered in SAM.gov and pursuing non-dilutive federal R&D funding. We submitted a Navy STTR Phase I proposal in 2026 in partnership with Virginia Tech's MICS Group.

Leadership

Charles W. McClish III

Founder & CEO

Designed the cell architecture, instruction set, and RTL. Built the cycle-accurate simulator, the DSP block library, the GNU Radio integration, and the placeKYT development environment. Took the design from concept through tape-out solo.

The Symbol

Six characters. One square. The complete architecture of a processor.

It started with a thought experiment: what is the simplest possible processor that can communicate with its neighbors? The answer was the flip-jump processor—a single-instruction machine that flips a bit and jumps to an address. The \ is flip. The ‾ is jump.

But simplicity alone isn't enough. The right balance came from adding just what was necessary. The = represents memory operations and comparisons. The \ becomes transformation. The + is arithmetic. The .* represents on-board memory—the cell stores its own program and data, executing any combination of instructions until it finally JUMPs to a neighbor.

The square represents the cell itself: self-contained, four faces, four neighbors. Everything the cell does and everything it is can be described with this diagram.

But there is more than meets the eye.

The five left-side characters form a face looking right—. is the ear, * the eye, \ the nose, = the mouth. The cell is awake. Active. Looking forward.

Now look at the right-side characters, ignoring the .*—another face, but with its eye closed. The cell at rest. This is the asynchronous nature made visible: fully active or fully off, instantly. No idle state. No wasted energy.

Simple units. Complex emergence. Like fungal networks or ant colonies—individual cells following simple rules, together producing behavior far greater than the sum of their parts.

Nothing more than necessary. Nothing less than sufficient.